asynx.dev Newsletter 2021/1

2021/1 newsletter includes progress between 2020-09-26 and 2021-01-09. This is the first newsletter.

News from us

  • Hello World! asynx.dev was born on 2020-09-06. This is our first Tweet.

Blog

  • (🇬🇧) If you are a Xilinx user working with Memory Interface Generator (MIG), check out our post about problems with init_calib_complete signal and hints. By Yunus ESERGÜN. This is our first blog post by the way.
  • (🇬🇧) Some of us work on corporate networks behind proxies and with self-signed SSL traffics. Check out this post if you want to work with pip and pipenv, and this one to use VS Code. Both by Alper YAZAR
  • (🇬🇧) Check out this post to learn about some basic stuff about Ethernet MII signals and see the MII problem that we observed while working with Zynq 7000 SoC with EMIO configuration. By Yunus ESERGÜN
  • (🇬🇧) You want to connect a serial device on a remote machine but you have only network access. Don’t worry, use socat to do serial-over-ethernet with cross platform support! Check out this post to do serial communication over TCP. By Anıl TIRLIOĞLU
  • (🇬🇧) Vitis is the new development framework for Xilinx devices. Check out our post to get started with Vitis acceleration flow for Zynq 7000 devices. By Anıl TIRLIOĞLU

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Notes

  • (🇬🇧) and (🇹🇷) denote English and Türkçe content, respectively.
  • This newsletter is published at most once a week.

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